The present invention relates to digital data-processing systems, and specifically concerns the generation and use of multiphase clock signals in a multiple-chip system.
At the heart of every digital data-processing system beats a clock which synchronizes almost every operation of the system. The processor executes instructions, parts of instructions, and parts of parts of instruction in step with the master clock. Buses regulate the flow of data from one unit to another according to the clock signals. The primal measure of a system's speed is the cycle time of its master clock.
Many events within the individual digital circuits of a data-processing system must occur in a particular sequence. For example, conventional data latches receive data, latch the data, and transfer it to an output in response to different clock signals whose proper sequence must be maintained over extremes of temperature, supply-voltage variation, and manufacturing tolerances from one chip to another. On a larger scale, storage registers must receive address and data signals in a predetermined order over these variations in operating conditions. Registers at different locations on a processor chip, and on different chips, must exchange sequential signals without overlap.
Many digital systems use a simple square-wave (single-phase) master clock signal for all circuits. One way to increase the effective speed of such a system is to use multiple clock phases, all at the same frequency. This technique allows the proper sequences to be enforced without increasing the operating speed of the functional logic circuits. However, conventional methods of generating and distributing multiphase clocks have significant disadvantages.
The simplest way to increase the speed of a digital system is to increase its raw clock frequency, thus decreasing the duration of each clock cycle. However, ensuring the proper sequence of events within the system sometimes requires that two events be separated by an entire clock cycle, so that unavoidable circuit-delay variations will not create race conditions.
One way to employ multiphase clocks in a digital system is to divide a single square-wave clock signal into multiple phases on a single master clock chip, each phase being a square wave having a predetermined relative time relationship to the others, and then distribute each phase separately to each card and chip in the system. This requires expensive and space-consuming additional clock lines and connections on backplanes and cards. Moreover, distributing these phases to a number of different functional cards and chips within a card degrades their relative timing so badly that much of the advantage of having multiple phases is lost.
Another method is to generate a single-phase master clock at a very high frequency, distribute it to each card and chip, then employ digital counter circuits on each chip to generate the separate phases. This method avoids the relative-timing problem, but it requires the distribution of extremely high frequencies from card to card and from one chip to another. Circuit structures for such frequencies are expensive and difficult to manufacture.
A further way to achieve multiple phases is known to the art. A single signal at the final frequency is distributed from the master clock to each chip, thus avoiding complex distribution circuits. Within each chip, a voltage-controlled oscillator and a phase-locked loop generate a high-frequency multiple of the incoming clock. Then counter circuits derive the multiple phases at the lower frequency. This expedient avoids high-frequency distribution, but it has the marked disadvantage of requiring a large area on each chip for these extra circuits. Moreover, such circuits frequently require off-chip filter components, which use circuit-card space and valuable pin connections for each chip.